1. Technical Field
The invention relates generally to a processor pipeline architecture with an intermittent power supply, and more particularly, to a method and system for retaining a logic state of such a processor pipeline.
2. Background Art
Pipelining is a standard feature in, e.g., a reduced instruction set computer (RISC) processor. In pipelining, a processor works on different steps of an instruction at the same time, so that more instructions can be executed in a shorter period of time. A practical problem with a pipeline type processor is data dependencies among different stages, which occurs when an instruction depends on the results of a previous stage.
Removal of power during the propagation of data from a stage to the next stage may make the data dependency problem even worse and cause a stall of the processor processing. Removal of power may be caused by an intermittent power supply, which is used when a regular stable power supply is not practical. In this situation, the processor needs to know the last valid logic state of the pipeline architecture to resume processing of an instruction after power is resumed. As such, the processor pipeline architecture needs to retain/remember the last logic state before power is removed. Current state of art technology does not provide a successful solution to this problem.
Based on the above, there is a need in the art for a solution to retain a logic state of a processor pipeline architecture.